NXP Semiconductors /MIMXRT1052 /IOMUXC /SW_MUX_CTL_PAD_GPIO_B1_05

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Interpret as SW_MUX_CTL_PAD_GPIO_B1_05

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

MUX_MODE=ALT0, SION=DISABLED

Description

SW_MUX_CTL_PAD_GPIO_B1_05 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: LCD_DATA17 of instance: lcdif

1 (ALT1): Select mux mode: ALT1 mux port: LPSPI4_SDI of instance: lpspi4

2 (ALT2): Select mux mode: ALT2 mux port: CSI_DATA14 of instance: csi

3 (ALT3): Select mux mode: ALT3 mux port: ENET_RX_DATA01 of instance: enet

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO21 of instance: flexio2

5 (ALT5): Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_B1_05

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